PCIe hardware description

This document is written as a companion to the Tegra30 TRM.

The Tegra PCIe controller provides a bridge from the internal AXI bus to PCIe controller registers and an internal bus known as FPCI. The controller contains 2 (Tegra20) or 3 (Tegra30) root ports, which are attached to this internal bus. The root ports bridge transactions onto the external PCIe buses, according to the FPCI bus layout and the root ports' standard PCIe bridge registers. The controller is accessible via a 1 GiB aperture of CPU-visible physical address space; all control register, configuration, IO, and MMIO transactions are made through this aperture.

The first 16 KiB (Tegra20) or 32 KiB (Tegra30) of the PCIe aperture are reserved for PCIe controller registers, and are laid out as follows:

The rest of the aperture exists to translate transactions from the CPU’s AXI bus onto the FPCI bus. This translation is completely configurable via 6 (Tegra20) or 9 (Tegra30) "BAR" registers in the AFI space. Each BAR specifies an AXI base address (which must reside within the 1 GiB PCIe aperture), an FPCI base address, a size, and other details. See the Tegra30 TRM for complete details of the BAR registers.

CPU-initiated transactions to the FPCI bus are translated into transactions on a PCIe bus by the root ports. The type of PCIe transaction generated is determined by the FPCI address. The address to PCIe transaction type mapping is hard-coded in hardware, and is described in the table below. Translated transactions are routed to a particular root port’s PCIe bus based on standard PCIe rules and root port BAR register content.

When an MMIO transaction is translated, the PCIe address is identical to the FPCI address.

When an IO transaction is translated, the PCIe address is the FPCI address minus the base address of the FPCI IO region, 0xfd_fc00_0000.

PCIe configuration transactions are generated by sending transactions to the FPCI bus regions listed in the previous sections. The lower bits of the FPCI transaction address encode the target PCIe bus, device, function, and register number.

For regular configuration transactions (which support registers < 256), the lower address bit mapping is as follows:

For extended configuration transactions, the lower address bit mapping is as follows:

Observe that this scheme is conceptually similar to the standard ECAM mapping, but not identical.

In practice, extended configuration transactions may be used for any register number. Extended configuration transactions to registers < 256 should behave identically to regular configuration transactions. However, this assertion has not received full validation by silicon designers.

On many x86 PC systems, the host controller, or PCIe root complex, responds to configuration transactions, and hence shows up on the PCIe bus as device 00:00.0. This is not the case on Tegra. All host controller registers must be accessed using the dedicated regions described previously in Aperture Layout.

Similarly, Tegra’s PCIe root ports do not respond to configuration transactions, and their registers must also be accessed through the dedicated regions described previously. However, the layout of these registers does conform to the standard.

The association between root ports and PCIe lanes is not fixed. The AFI "PCIe CONFIG" register contains a field to configure which lanes are attached to each root port. Each SoC supports a specific set of combinations, which are listed below:

Tegra20:

Tegra30: